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ATE:Vision 2020

2nd IEEE International Workshop on
Automated Test Equipment: Vision ATE 2020

October 30-31, 2008
Santa Clara Convention Center
Santa Clara, CA, USA

Held in Conjunction with ITC Test Week (ITC 2008)

http://www.ATEVision.com

CALL FOR PAPERS
Scope -- Submissions -- Key Dates -- Committees -- Additional Information

Scope

The workshop will examine where the ATE industry is heading in the near-term as well as in the long-term. Integrated circuits get denser, larger, and faster and more heterogeneous. As the number of dies in a single package increases, so does the test quality target. Certain dies require Known-Good-Die (KGD) quality levels, whereas more complex failure modes already challenge our yield learning curves.

These issues, when added to increasing Cost-Of-Test (COT), Time-To-Volume (TTV), and Time-To-Market (TTM) pressures, driven by today’s high-volume market applications, pose significant challenges to the ATE industry. To meet those challenges the industry needs to innovate in areas such as test methodologies, interconnection technologies, architectures, and Design-For-Testability (DFT) and Design-For-Manufacturability (DFM) technologies.

The goal of this workshop is to create an informal forum to discuss those innovations relevant to ATE developers and users. We are looking for solutions to the issues of 2012 and beyond, not those of 2009. What are companies doing today to address needs five years out? What are the test solutions for new technologies such as quantum computing, bio-computing, or cloud computing? Are our present technologies adequate for the future, and what should we be doing to close the gaps? We are not looking for a standard paper filled with results, we are looking for speculation. And 2020 refers to vision: you do not need to predict what testing will be like that far in the future!

Representative topics include, but are not limited to:

  • Design for Testability (BIST, BISR)
  • Test methods for future defects
  • ATE/EDA Link
  • High-speed IO ATE
  • Low-cost ATE
  • RF ATE
  • ATE for Statistical Test

Submissions

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To present at the Workshop, authors are invited to submit presentation proposals. The proposals may be draft presentations, extended abstracts (500 words), or full papers. Each submission should include: title, full name and affiliation of all authors, a short abstract of 50 words, and keywords.  Also, identify a contact author and include a complete correspondence address, phone number, fax number, and e-mail address.

Submit a copy of your presentation proposal by Postscript, or PDF, via E-mail.  Proposals for panel discussions are also invited. Submissions are due no later than August 22, 2008. Submit your proposals to:

Scott Davidson, Sun Microsystems   
E-mail: scott.davidson@sun.com 
Tel: +1-408-992-9113

Authors will be notified of the disposition of their presentation by September 19, 2008.

Authors of accepted presentations must submit the final presentation by October 3, 2008 for inclusion in the Workshop Notes, which will be provided to the attendees on a memory stick. Optionally, an extended abstract or paper can also be included in the notes.

Key Dates

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Submission deadline: August 22, 2008
Notification of acceptance: September 19, 2008
Final copy deadline: October 3, 2008

Committees
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General Chair
E. Volkerink, Verigy

General Co-Chair
Y. Zorian, Virage Logic

Program Chair
S. Davidson, Sun Microsystems

Program Co-Chair
M. Kondrat, Cascade Microtech

Panel Chair
A. Khoche, Verigy

Finance Chair
R. Chandramouli, ARM                

Publicity Chair
A. Gold, Advantest

Webmaster
F-F Ferhani, Broadcom

Program Committee

R. Barth, Numonyx
P. Burlison, Inovys
K. Cho, Nvidia
C. J. Clark, Intellitech
W. Fister, Micron
G. Fleeman, Advantest
B. Gage, Teradyne
M. Hafed, DFT Microsystems
B. Price, NXP
R. Kapur, Synopsys
D. Keezer, GeorgiaTech
R. Lesnikoski, Sun Microsystems
P. Mantri, Sun Microsystems
J. Moreira,  Verigy
P. Muhmenthaler, Infineon
M. Roos, Roos Instruments
J. Rivoir, Verigy

N. Touba, University of Texas
C.W. Wu, Tsing Hua University

Additional Information
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General Information

Erik Volkerink, Verigy
E-mail: erik.volkerink@verigy.com
Tel: +1-408-864-7661

For more information, visit us on the web at: www.ATEVision.com

ATE Vision 2020 is sponsored by the IEEE Computer Society Test Technology Technical Council (TTTC).


IEEE Computer Society- Test Technology Technical Council

TTTC CHAIR
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

SENIOR PAST CHAIR
Yervant ZORIAN
Virage Logic - USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

TTTC 2ND VICE CHAIR
Chen-Huan CHIANG

Lucent Technologies
- USA
Tel. +1-732-949-5539
E-mail chenhuan@lucent.com

FINANCE
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

DESIGN & TEST MAGAZINE
Tim CHENG
University of California, Santa Barbara - USA
Tel. +1-805-893-72942
E-mail timcheng@ece.ucsb.edu

TECHNICAL MEETINGS
Chen-Huan CHIANG

Lucent Technologies
- USA
Tel. +1-732-949-5539
E-mail chenhuan@lucent.com

TECHNICAL ACTIVITIES
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica - Mexico
Tel.+52-22-470-517
E-mail champac@inaoep.mx

ASIA & SOUTH PACIFIC
Hideo FUJIWARA
Nara Institute of Science and Technology - Japan
Tel. +81-74-372-5220
E-mail fujiwara@is.aist-nara.ac.jp

LATIN AMERICA
Marcelo LUBASZEWSKI
Federal University of Rio Grande do Sul - Brazil
Tel. +34-93-401-6603
E-mail luba@vortex.ufrgs.br

NORTH AMERICA
William R. MANN
Tel. +1-949-645-3294
E-mail william.mann@ieee.org

COMMUNICATIONS
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Virage Logic - USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

 

PAST CHAIR
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

TTTC 1ST VICE CHAIR
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

SECRETARY
Christian LANDRAULT
LIRMM - France
Tel. +33-4-674-18524
E-mail landrault@lirmm.fr

INTERNATIONAL TEST CONFERENCE
Doug J. YOUNG
SV Probe Inc.
- USA
Tel.
E-mail dyoung@svprobe.com

TEST WEEK COORDINATION
Yervant ZORIAN
Virage Logic - USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

TUTORIALS AND EDUCATION
Dimitris GIZOPOULOS

University of Piraeus
- Greece
Tel. +30-210-414-2372
E-mail dgizop@unipi.gr

STANDARDS
Rohit KAPUR

Synopsys
- USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

EUROPE
Zebo PENG
Linköping University - Sweden
Tel. +46-13-282-067/-281-000
E-mail zpe@ida.liu.se

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut - Lebanon
Tel. +961-1-341-952
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

ELECTRONIC MEDIA
Alfredo BENSO
Politecnico di Torino - Italy
Tel. +39-011-564-7080
E-mail alfredo.benso@polito.it


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